DPFFs: C2MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling

We propose two master-slave flip-flops (FFs) that utilize the clocked CMOS (C2MOS) technique with an internal direct connection along the main signal propagation path between the master and slave latches and adopt an adaptive body bias technique to improve circuit robustness. C2MOS structure improves the setup margin and robustness while providing full compatibility with the standard cell characterization flow. Further, the direct path shortens the logic depth and thus speeds up signal propagation, which can be optimized for less power and smaller area. Measurements from test circuits fabricated in 130 nm technology show that the proposed FF operates down to 60 mV, consuming 24.7 pW while improving the propagation delay, dynamic power, and leakage by 22%, 9%, and 13%, respectively, compared with conventional FFs at the iso-output-load condition. The proposed FFs are integrated into an 8×8 FIR filter which successfully operates all the way down to 85 mV

New Key Management Approach for Broadcast and Multicast Services

Key management for multicast and broadcast services has been the subject of extensive research for more than 10 years. Difficulty to find an appropriate security mechanism lies in the fact that a very high number of users consume streamed protected contents simultaneously. 3GPP, IEEE and ETSI security experts have developed various Key Management Schemes (KMS) that focus on the reduction of transmission overhead caused by distribution of associated key material over broadcast and interaction channels. In this paper, we propose new approach to key management, called 2-way Hash Chains Scheme (2HCS), which effectively reduces the number and the size of keying messages and shows considerable performance improvement over its predecessors

System-Level Simulator for the W-CDMA Low Chip Rate TDD System Ý

Abstract — A system-level simulator for the W-CDMA Low Chip Rate TDD system is developed. This simulator considers multi-cell and multi-user environmets and SIR-based power control. For accurate and reliable results, inner-cell and outer-cell interference is modeled by chip-level spreading and an SIR estimation scheme is used. From this simulator, system-level performance is evaluated in terms of the received SIR distributions for downlink and uplink. The degradation probability is also introduced as a QoS indicator in system-level. I